In semiconductor memory, data is written to memory for storage until read at a later time. Writing data typically involves issuing a write command to the memory and also providing the write data that is to be written to memory. The write data can be provided to the memory at a time after the write command is issued to allow operations internal to the memory device to occur for the write command to be executed. The timing between the issuance of the write command and its write data to the memory are related by “write latency.” As known, write latency is the delay, in clock cycles, from the issuance of a write command to the latching of the first write data. An example of typical write latency is 12 clock cycles of the Clk signal.
Correct timing of internal timing signals generated in response to external command and clock signals is critical for proper operation of the memory. Complicating the generating of correctly timed internal signals is the relatively high frequency of memory clock signals. For example, memory clock signals can exceed 1 GHz. Further complicating the matter is that multi-data rate memories can provide and receive data at a rate higher than the memory clock signal. With respect to write commands, a write clock signal may be provided to the memory for correctly timing the rate at which write data is received by the memory. Correctly timing internal write operations relative to the receipt of the write command, write data, memory clock signal and write clock signal is required to properly complete a write operation.
The traditional method of timing the write data with the memory clock is modeling both the write clock path and the system clock path to have the same propagation delay. With higher-speed clock signals, however, the propagation delay of the clock paths may be on the order of several clock cycles, thus, preventing write throughput from being optimized. Additionally, the propagation delay can often vary due to power, voltage, and temperature conditions. In cases where the memory clock is a lower frequency than the write clock, tight phase control between the memory clock and the write clock is necessary for correct operation, which is complicated by the total propagation delay time and the variation in the delay due to power, voltage, and temperature conditions.